Subthreshold Modeling of GAA MOSFET Including the Effect of Process-Induced Inclined Sidewalls

Abstract

The impact of process-induced inclination angle ( \theta ) of nonvertical sidewalls of the fabricated quadruple gate (QG) metal-oxide-semiconductor field-effect transistor (MOSFET) on subthreshold characteristics has been analytically modeled and analyzed using the equivalent width, equivalent oxide, and coupling between the two equivalent double gate (DG) MOSFETs. A quasi-3-D scaling length model has been formulated accounting \theta and corner gates, which was subsequently applied to derive the channel center potential, threshold voltage, subthreshold current, subthreshold swing (SS), and noise margin (NM) for subthreshold logic applications of trapezoidal (Tz) gate-all-around (GAA) MOSFETs. The newly formulated models were successfully verified using TCAD calibrated to the experimental results of our fabricated QG-MOSFETs. We found that for channel length, {L} {g} = 50 nm, Fin height, {H} {Fin} = 20 nm, and Fin top width, {W} {top} = 10 nm, the potential barrier of TzGAA MOSFET falls by 4.7% at \theta =30\circ compared to rectangular cross section, thereby, deteriorating the short-channel immunity of the device. The SS roll-up, threshold voltage roll-off, drain induced barrier lowering (DIBL), voltage transfer curve (VTC) of subthreshold CMOS inverter, and NM degradation due to inclined sidewalls have been calculated using the developed models. According to the scaling theory, the minimum {L} {g} for a NM degradation of 5 mV is 30.5 nm corresponding to \theta =0^\circ , and 42.7 nm at \theta = 30° for {H} {Fin} = 20 nm.