One transistor floating body RAM performances on UTBOX devices using the BJT effect

Abstract

This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1T-DRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.