Analysis, reduction and avoidance of crosstalk on VLSI chips

Abstract

As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on-chip timing and even functionality. A method is presented to analyze crosstalk while taking into account timing relationship and timing criticality between coupling wires. The method is based upon the geometrical layout of the wires (adjacency), the signal slopes on the wires (circuit driving capability) and timing considerations. Based on these wire characteristics, a pattern driven routing tool imbeds the crosstalk critical nets in non-adjacent wiring tracks for crosstalk avoidance. The pattern driven routing capability may also be used for rerouting crosstalk critical nets of an already existing routing for crosstalk reduction. The crosstalk analysis and the routing tool described in this paper were used in three generations of VLSI processor chip designs for IBM's S/390 computers, always resulting in crosstalk-resistant hardware.