Abstract
The remarkable breakthroughs in deep learning have led to a dramatic thirst for computational resources to tackle interesting real-world problems. Various neural network processors have been proposed for the purpose, yet, far fewer discussions have been made on the physical synthesis for such specialized processors, especially in advanced technology nodes. In this paper, we review several physical synthesis techniques for advanced neural network processors. We especially argue that datapath design is an essential methodology in the above procedures due to the organized computational graph of neural networks. As a case study, we investigate a wafer-scale deep learning accelerator placement problem in detail.
Cite
CITATION STYLE
He, Z., Liao, P., Liu, S., Ma, Y., Lin, Y., & Yu, B. (2021). Physical Synthesis for Advanced Neural Network Processors. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 833–840). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1145/3394885.3431625
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