ADC-based Wireline Transceiver

Abstract

• ADC-Based PAM4 Transceivers have gained traction at 56Gbps/112Gbps, especially for Long-Reach Applications • ADC-Based Transceivers uses hybrid analog &DSP Equalization (TX-FFE, RX-CTLE, DSP) • ADC Non-idealities (BW, Nonlinearity, Noise, Jitter, Metastability) need to be accurately captured and modeled • The design of 56Gbps RX Front-End, ADC Sampling FrontEnd, SAR-ADC, RX Clocking, and DSP are described • ADC Calibration, EQ Adaptation, and CDR schemes are described • ADC-Based architecture can scale to 112Gbps, but BW and EQ scaling causes significant power.