237 Gbit/s unrolled hardware polar decoder

Abstract

A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented using a field-programmable gate array. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.