Resilience and yield of flip-flops in future CMOS technologies under process variations and aging

Abstract

In this study, the failure rate of flip-flops in future 16 nm complementary metal-oxide-semiconductor (CMOS) technologies is investigated. Using transistor level Monte Carlo simulations, the authors studied the influence of process variations and long term aging on the yield. The statistical distribution of the switching time (clock-to-Q delay) is shown to be highly asymmetric compared to a Gaussian distribution leading to a drastically enhanced fraction of very slow or metastable samples. Moreover, the failure rates will rise additionally during the device lifetime because of aging effects. To improve the yield the authors investigated several possible countermeasures including enhanced supply voltage or ensuring larger data-to-clock times as well as process and circuit optimisation. © 2014 The Institution of Engineering and Technology.