An efficient high speed squaring and multiplier architecture using yavadunam sutra and bit reduction technique

Abstract

Vedic Mathematics, an ancient Indian technique can be used to solve any arithmetic problems in an easy and simple way. A novel high speed Vedic squaring and multiplier unit is designed using the principles of Yavadunam sutra and the bit reduction technique is projected in this paper. The complexity of the multiplier is reduced as the bit reduction technique is employed and later the Yavadunam sutra is implemented for the calculation of the deficiency. The size of the proposed N bit multiplier is reduced to N-1 bit and also considerable speed improvement is achieved. The architecture is designed and realized using Xilinx Spartan FPGA and synthesized using 90nm and 180nm technology synopsys device.