A 250Ks/s, 0.8V ultra low power successive approximation register adc using a dynamic rail-to-rail comparator

Abstract

A low voltage low power successive approximation register (SAR) analog-to-digital converter (ADC) based on a novel rail-to-rail comparator is proposed in this paper. The power consumption of the comparator is significantly reduced through dynamic operation while the speed is augmented by using an efficient regenerative latch. No biasing circuits are needed and there are no floating nodes in the comparator throughout the conversion process. The digital-to-analog converter (DAC) is formed from a binary array of MIM capacitors. The 250KS/s ADC implemented in a 0.18μm process consumes only 1.35μW of power at a supply voltage of 0.8V. © IEICE 2010.