Air-gap formation during IMD deposition to lower interconnect capacitance

Abstract

The use of air-gaps between interconnect metal lines to reduce interconnect capacitance has been explored. Simulations were performed to determine the reduction in capacitance obtainable using air-gaps. The formation of air-gaps in the isolation oxide between metal lines was simulated using Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). The capacitance of the SPEEDIE profiles was then extracted using Raphael (an electrical analysis simulator from TMA). The feasibility of air-gaps was also demonstrated experimentally. Fabricated air-gap structures exhibited a 40% reduction in capacitance when compared to a HDP-CVD oxide gap-fill process with K = 4.1. Additionally, the air-gap structures did not exhibit any appreciable leakage current.