Experimental determination of interface trap density and fixed positive oxide charge in commercial 4H-SiC power MOSFETs

Abstract

We measure interface trap density near the conduction band edge and fixed oxide charge in commercial, packaged, 4H-SiC 1.2 kV planar Power MOSFETs. These traps determine the device threshold voltage, performance, and reliability. The subthreshold slope is used to extract interface trap density at the SiO2-SiC interface near the conduction band edge from three vendors, which varies from 5.8 × 1012to 9.3 × 1012cm-2·eV-1. Good agreement is obtained with threshold voltage measurements from 25°C to 150°C as devices with the highest interface trap densities exhibit the largest threshold voltage reduction over temperature. Fixed positive oxide charge, Not, balanced with interface traps and substrate doping, varies from 3.3×1012cm-2to 3.7×1012cm-2. At high temperatures, electrons captured in interface traps emit to the conduction band and lower the threshold voltage together with fixed oxide charges, which are as high as interface trap densities. Thus, device design should be considered for a suitable threshold voltage to ensure the device does not operate in a Normally-ON condition and to protect against gate voltage surges. Therefore, more focus on characterization and reduction of the interface trap density and fixed oxide charge is needed to enable further improvement in effective electron mobility of SiC MOSFETs.