Low-Power Logic-in-Memory Complementary Inverter Based on p-WSe2 and n-WS2

Abstract

Transition metal dichalcogenides have been considered as candidate materials to construct logic-in-memory devices for realizing non-von-Neumann architecture. Thus, reducing the power consumption is extremely critical for their applications in big data and artificial intelligence. Here, a low-power logic-in-memory device is demonstrated by constructing complementary inverter with p-WSe2 and n-WS2 transistors. By engineering the interface states between WSe2 (WS2) and substrate artificially, non-volatile memory with resistance ratio of 104 and 103 after 500 s are achieved in individual WSe2 and WS2 transistors, respectively. Furthermore, a complementary inverter with a retention time longer than 500 s is realized by connecting p-WSe2 and n-WS2 transistors. More importantly, the static operating source-drain current Ids of this inverter is around 0.5/0.1 nA at low/high resistance states with source-drain voltage Vds = 5 V, and the hysteresis window is located around 0 V, both of which can reduce the energy consumption dramatically and leads to the low operation power. This work provides a convenient strategy to build a non-von-Neumann device toward post-Moore information processing technology.