Optimized VLSI design of 2-Bit magnitude comparator using GDI technique

Abstract

In the modern VLSI, the need for optimizing design constraints has become a major concern both at schematic level as well as layout level. Mux based approach has been extensively used due to the efficient implementation of Mux using Gate Diffusion Input (GDI). Several designs have been studied and finally a Mux based Magnitude Comparator is proposed with optimized VLSI design constraints. All the possibilities of design using mux with wide variety of primary inputs as selection inputs of mux have been studied and the best design which has lead to minimal transistor count was proposed.In this paper, GDI technique has been implemented in 250 nm process technology using TANNER S-EDIT. There is 70%, 33% and 9% reduction in transistor count in comparison with existing GDI comparators respectively.