Abstract
We implement a JPEG2000 encoder based on a hardware/software co-design methodology. We emphasize on the concurrent execution of hardware accelerator IPs and software running on the CPU. In an SOC platform, sequential hardware acceleration of DWT and EBCOT Tier-1 coding gives us 70% reduction in total execution time. The proposed concurrent scheme achieves additional 14% saving. We describe our experience in bringing up such a system. © 2005 IEEE.
Cite
CITATION STYLE
Yen, W. C., Chen, A. C., Liu, P. S., & Lin, Y. L. (2005). A hardware/software-concurrent JPEG2000 encoder. In 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) (Vol. 2005, pp. 181–184). https://doi.org/10.1109/VDAT.2005.1500050
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