Evaluating optimized implementations of stream cipher ZUC algorithm on FPGA

Abstract

Compared with block ciphers, stream ciphers are more efficient when implemented in hardware environment, like Field Programma-ble Gate Array (FPGA). In this paper, we propose three optimized schemes in the FPGA implementation of a novel and recently proposed stream cipher, ZUC, which is a new cryptographic algorithm proposed for inclusion in the '4G' mobile standard called LTE (Long Term Evolution). These three schemes are based on reusing area of S-box, calculation of CSA tree and pipelined architecture to implement ZUC on FPGA respectively. We also evaluate each optimized scheme in terms of performance and consumed area in Xilinx FPGA device to compare their actual hardware efficiency. According to the evaluation results, the third scheme, namely pipelined architecture implementation, optimizes hardware implementation of ZUC for the best performance and achieves a throughput of 7.1 Gbps using only 575 slices by speeding up the keystream generating on FPGA. To our knowledge, it is an extremely efficient hardware implementation of ZUC at present. Moreover, it also shows that ZUC is quite flexible to balance different throughput with consumed area. © 2011 Springer-Verlag.