Analysis of UCIe 48/64-GT/s Electrical Links

Abstract

The Universal Chiplet Interconnect Express (UCIe) standard, developed with significant contributions from the authors, has emerged as a key solution for chiplet-based architectures, offering enhanced scalability, efficiency, and performance. This article presents an analysis of UCIe electrical links operating at data rates of 48 and 64 GT/s. Leveraging our experience in the UCIe standard since its inception, we explore the technical advancements that enable these data rates, including improvements in signal integrity and power efficiency. The analysis provided in this article served as critical data inputs for the UCIe consortium, leading to the subsequent evolution of the standard. We examine link performance and reliability through detailed modeling of failure probability distributions, highlighting the challenges and solutions associated with error management and fault tolerance. Design considerations for extending UCIe data rates are discussed, along with future directions for the standard.