Sub-kT/q subthreshold-slope using negative capacitance in low-temperature polycrystalline-silicon thin-film transistor

Abstract

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O 3 (PZT)/ZrTiO 4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at'0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm 2 /Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.