Abstract
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification. © 2010 Springer-Verlag.
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CITATION STYLE
Brayton, R., & Mishchenko, A. (2010). ABC: An academic industrial-strength verification tool. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6174 LNCS, pp. 24–40). Springer Verlag. https://doi.org/10.1007/978-3-642-14295-6_5
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