A new configuration of three-level ZSI using transistor clamped topology

Abstract

In this paper, a three-level ZSI (impedance source inverter) based on transistor clamped theory is proposed. It uses the least number of switch counts and associated gate circuitry among all existing topologies of three-level ZSI without any performance degradation. The existing three-level ZSI topologies require three power switches to be turned ON for upper-lower shoot-through (ULST), and four power switches to be turned ON for full dc-link shoot-through (FST). However, with the proposed configuration, upper–lower shoot-through (ULST) and full dc-link shoot-through (FST) is inserted by turning ON only two power semiconductors. A comparison between diode clamped, transistor clamped, and t-type is presented. The proposed topology can realize any of the existing sine-triangle- or space vector-based PWM (pulse width modulation) schemes, and all existing configurations of three-level ZSI can merge into the proposed inverter configuration.