Pipelined photonic analog-to-digital converter

Abstract

Electronic analog to digital converters (EADCs) face serious challenges when the root mean square timing jitter of the sampling pulse is less than a femtosecond. This restriction limits the maximum allowable sampling frequency of an EADC. In photonic analog-to-digital conversion (PADC), using a mode locked laser as a sampling source limits the sampling frequency timing jitter only at sub-femtosecond levels. The current architectures for PADC use photonic techniques either for sampling or for quantization. Consequently, current PADC architectures are not suitable for higher frequency applications because of the limitations of their electronic components. In this paper, the feasibility of implementing concept architecture for a fully photonic pipelined ADC is analyzed and evaluated to provide a design for an 8-bit pipelined PADC, the performance of which is investigated through modeling and simulation. The 8-bit pipelined PADC's effective number of bits is shown to be 4.34 bits at 200 gigasample per second.