Design of Energy Efficient Static Level Restorer Based Half Subtractor using CNFETs

Abstract

The demand for portable appliances and electronic equipment with technology is increasing rapidly with improvement in Very Large Scale Integration (VLSI) design. Arithmetic circuits are considered as a critical factor for the development and design of microprocessors, Digital Signal Processing (DSP), neural networking, etc. Arithmetic circuits such as adders, subtractors, compressors, multipliers, and so on are considered prime significance for the enhancement of power consumption and energy efficiency. In this paper, a 13T complementary level restorer based half subtractor using Carbon Nanotube Field Effect Transistor (CNFET) technology is presented. A complementary level restorer is added to the subtractor design such that it increases the dynamic power. The 13T half subtractor design is carried out through the HSPICE tool with 32 nm CNFET technology. Different metrics are carried out such as average power, delay, Power consumption, temperature stability, Energy Delay Product (EDP), and compared to the existing circuit designs. The proposed half subtractor design using CNFET technology is superior compared to its counterparts in terms of delay, power, and energy efficiency.