A Hierarchical Self-Interference Canceller for Full-Duplex LPWAN Applications Achieving 52-70-dB RF Cancellation

Abstract

We present a radio frequency self-interference (SI) canceller chip for low-power wide area network (LPWAN) basestations. To enhance the cancellation capability without necessitating unreasonable resolution, power consumption, and area, we introduce a hierarchical cancellation technique using a nested vector modulator (VM) implementation. Nesting a 7-b and two 6-b stages, a 16-b theoretical and >13-b measured resolution is obtained per tap. LPWAN channels have large group delay and group delay spread in tens of ns, and a requirement for >100 dB of analog SI cancellation. To enable large ON-chip group delay, we leverage frequency translation circuits, and in comparison to prior art, decouple impedance matching requirement from tap delay implementation to realize range/resolution from 16 ns/33 ps to 80 ns/150 ps. We demonstrate 64 dB of RF SI cancellation over 0.8-MHz bandwidth (BW) with a three-tap implementation for an LPWAN wireless channel. For more controlled environments, up to 70-dB cancellation is shown. Each tap occupies 0.21 mm2 of area and consumes 12.3 mA of current with a 1.2-V supply voltage. The whole chip occupies 1.2 mm2 and consumes 44.28 mW of power in a 65-nm CMOS process.