Circuit level low power design, implementation and performance evaluation of different SRAM bit cell configurations operating at ultra-low voltage

Abstract

Read and write battle and scaling limitations in standard 6T SRAM, the insufficient subthreshold performance of conventional 7T SRAM and more standby power of 8T SRAM demand the researchers o develop more stability, energy efficient, high speed and better performance memories for market demand. Low power subthreshold region operated 7T and 8T with read assist SRAMs are designed and implemented at an operating voltage of 0.1V. A grounded gate terminal of the cross-coupled inverter of the memory unit increases the stability and performance during the read as well as in write operations with reduced power consumption and delay. Nevertheless, the number of the transistors increased, the proposed designs reduce the power and delay with ground shorted gate terminal in one of the inverters of memory unit. The power and input to out delay of the proposed memory cells analyzed and elaborated with reference standard 6T, conventional 7T, and conventional 8T SRAM cells.