Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

Abstract

This paper describes a reconfigurable architecture for an on-board processor to be used in space exploration critical systems. It relies on, a dynamically reconfigurable multi-accelerator hardware architecture that provides transparent reconfiguration and scalable performance, dependability, and power consumption, at run-time. The architecture is integrated under an RTEMS operating system, which manages reconfiguration and fault mitigation in a fully-compatible way with space requirements. In this work, the proposed processor is used to implement a vision-based navigation system, providing fully autonomous adaptation to different phases of a space mission timeline or events that the spacecraft may encounter during its lifespan. Results show that reconfigurability enables the practical usage of Commercial Off-The-Shelf (COTS) Multiprocessor Systems-on-Chips (MPSoCs) in real scenarios.