Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width

Abstract

We investigate the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET) with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.