Analysis of threshold voltage and drain induced barrier lowering in junctionless double gate MOSFET using high-κ gate Oxide

Abstract

The change of threshold voltage and Drain Induction Barrier Lowering (DIBL) is observed when high dielectric constant material is used as gate oxide of the junctionless double gate (JLDG) MOSFET. For this purpose, an analytical threshold voltage model is proposed using the first term of the series-type potential model derived from the Poisson equation. The results of the model presented in this paper are in good agreement with threshold voltages derived from TCAD. Using this model, the threshold voltage and DIBL were observed for the channel length, the silicon thickness, and the gate oxide thickness with the dielectric constant as a parameter. As a result, when a high-κ material was used as a gate oxide, the threshold voltage increased but the rate of change with respect to channel size and oxide thickness decreased. The DIBL is inversely proportional to the dielectric constant, and the DIBL was as small as 20 mV/V even at a channel length of 15 nm when the dielectric constant was 30. In the case of using HfO2/ZrO2 (κ=25), the rate of change of threshold voltage for oxide thickness was about 1/5 smaller than SiO2 (κ=3.9). The rate of change of DIBL for oxide thickness in the case of La2O3 was about 1/4 smaller than SiO2 (κ=3.9). The use of the high-κ oxide film may increase the design margin for the oxide thickness variation.