DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless (Si JL-GAA) transistor

Abstract

With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model. This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity. The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversionmode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV/decade which approaches the ideal value, an Ion/Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV/V.