Slotted vias for dual damascene interconnects in 1Gb DRAMs

Abstract

A novel interconnect scheme is presented which has been used to significantly reduce the chip size of an 1Gb SDRAM chip. The key element is the use of slotted vias for low resistance horizontal interconnects. This allows to combine low capacitance/high resistance lines with low resistance/high capacitance lines. The slotted vias are realized by a dual damascene integration scheme without adding an additional mask level or process cost with excellent continuity yield and good electromigration performance.