An offset-tolerant current-sampling-based sense amplifier for sub-100nA-cell-current nonvolatile memory

Abstract

Decreasing read cell current (ICELL) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and VDD scaling while keeping the same threshold voltage (VTH), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1-2] to achieve smaller area-per-bit; 2) lower-VDD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller ICELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (CBL) mismatches and 2) VTH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-ICELLNVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7x faster read speed than previous SAs for sensing small ICELL. A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logic-compatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA ICELL. Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing. © 2011 IEEE.