Balanced XOR/XNOR circuits using CNTFET

Abstract

In this work, a standard design methodology in different logic styles using Carbon Nano Tube field effect transistor is proposed to construct Balanced XOR/XNOR circuit. The Proposed methodology is build on different basic cells to optimize area, power dissipation and delay. The circuits for Balanced XOR/XNOR can be designed with selecting a Elementary basic cell including two independent inputs and two complementary outputs. The basic cell is then combined with various correction and optimization techniques to build a perfect XOR/XNOR circuit to avoid weak zero and week one at the output. Simulation results of the proposed circuits shows better performances in terms of delay, power and PDP. The proposed circuits are evaluated using cadence virtouso.