Combined skewed CMOS Ring Oscillator

Abstract

A combined skewed ring oscillator by different type of delay stages is presented. This paper aims to drive a high stable and relatively high frequency but still use a full transistor circuit for ring oscillator with combined delay stages and skewed connections. First we propose two types of common inverters then calculate their delay time and analysis their dependence of delay time to variation of power supply voltage. The simulation results verify that delay time of these two CMOS inverters show opposite behaviour versus power supply changing. So a combined structure can obtain more appropriate frequency stability versus power supply noise. Also in order to increase oscillation frequency we have used the negative skewed delay connections. The simulation results using HSPICE for 0.18 µm CMOS shows a good agreement with analysis results. In addition in this paper the mathematical justification for improved functioning of this combined skewed ring oscillator has been proved. This justification shows appropriate agreement with the simulation results. From mathematical point of view the proposed ring oscillator has better frequency stability in comparison with other types of ring oscillators. In fact, the oscillation frequency sensitivity to supply voltage noise is reduced considerably.