A System-on-a-Chip Design of the AES Cryptographic System

Abstract

It is now very common to have SoC-powered IoT devices due to their low power consumption. This paper proposes a low-cost SoC implementation of the AES algorithm for resource constrained devices. The AES cryptographic module is based on a four-stage sub-pipelined architecture for encryption/decryption of all the standard key sizes (128, 192 and 256 bits) of AES. An on-the-fly key generator was implemented, making use of a single 32-bit XOR together with an8-deep shift register as the main components to compute round keys. The RTL of the architecture was designed using Verilog HDL and simulated with ModelSim. Also, a parallel and resource-shared MixColumn/Inverse MixColumn module was implemented to ensure a short critical path of the design. Synthesis of the proposed AES hardware implementation was done with Synopsys Design Compiler using the 180nm TSMC cell library. AES has been in use since the year 2001, when it replaced the DES algorithm. Most implementations in the past have been done in the software domain. However, it was discovered that the hardware implementation of AES is far better than its software counterpart for reasons of robustness and speed. Also, by using a four-stage pipeline, the proposed architecture is able to achieve a small area while providing a high throughput needed for the fast propagation of data. The proposed architecture achieved a low area of 16.1K NAND2 gate equivalent.A memory unit of size, 9.152KB was implemented to cater for the S-Box/Inverse S-Box modules. The maximum frequency of the design was 621.12MHz, which resulted in average throughputs of 7.15Gbps, 6.06Gbps and 5.26Gbps for 128-bit, 192-bit and 256-bit key lengths respectively. The proposed SoC–based AES cryptographic systemcan be applied to resource constrained devices that require high-performance as well as robust security, such as IoT devices.