A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks

Abstract

Capacitor-based in-memory computing (IMC) SRAM has recently gained significant attention as it achieves high energy-efficiency for deep convolutional neural networks (DCNN) and robustness against PVT variations [1], [3], [7], [8]. To further improve energy-efficiency and robustness, we identify two places of bottleneck in prior capacitive IMC works, namely (i) input drivers (or digital-to-analog converters, DACs) which charge and discharge various capacitors, and (ii) analog-to-digital converters (ADCs) which convert analog voltage/current signals into digital values.