A bus encoding scheme for crosstalk elimination in high performance processor design

Abstract

Crosstalk effect leads to increases in delay, power consumption, and in the worst case scenario, to inaccurate results. With the scale down of technology to the deep sub-micron level, the crosstalk effect between adjacent wires becomes more and more serious, especially between long on-chip buses. In this paper, we propose a deassembler/assembler technique to eliminate undesirable crosstalk effects on bus transmission. By taking advantage of the prefetch process, where the instruction/data fetch rate is always higher than the instruction/data commit rate, the proposed method incurs almost no penalty in terms of dynamic instruction count. In addition, when the bus width is 128 bits, the required number of extra bus wires is only 7 compared to 85 needed in [4]. Copyright © 2007 IEEE.