An adaptive analytic FPGA placement framework based on deep-learning

Abstract

In this work, a Convolutional Encoder-Decoder (CED) is utilized to significantly reduce placement runtimes for large, high-utilization designs. The proposed CED uses features available during the early stages of placement to predict the congestion present in subsequent placement iterations including the final placement. This congestion information is then used by the placer to improve decision making leading to reduced runtimes. Experimental results show that reductions in placer runtime between 27% and 40% are achievable with no significant deterioration in quality-of-result.