On the characterization and separation of trapping and ferroelectric behavior in HfZRO FET

Abstract

N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of ID–VG hysteresis, the hysteresis versus subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the FE layer responsible for charge trapping during device operation is characterized. Transient ID–VG measurements are introduced to facilitate differentiating between trapping and FE behavior during subthreshold slope measurements.