Techniques to reduce π/4-parity-phase circuits, motivated by the ZX calculus

Abstract

To approximate arbitrary unitary transformations on one or more qubits, one must perform transformations which are outside of the Clifford group. The gate most commonly considered for this purpose is the T = diag(1,eiπ/4) gate. As T gates are computationally expensive to perform fault-tolerantly in the most promising error-correction technologies, minimising the “T-count” (the number of T gates) required to realise a given unitary in a Clifford+T circuit is of great interest. We describe techniques to find circuits with reduced T-count in unitary circuits, which develop on the ideas of Heyfron and Campbell [10] with the help of the ZX calculus. Following Ref. [10], we reduce the problem to that of minimising the T count of a CNOT+T circuit. The ZX calculus motivates a further reduction to simplifying a product of commuting “π/4-parity-phase” operations: diagonal unitary transformations which induce a relative phase of eiπ/4 depending on the outcome of a parity computation on the standard basis (which motivated Kissinger and van de Wetering [12] to introduce “phase gadgets”). For a number of standard benchmark circuits, we show that these techniques - in some cases supplemented by the TODD subroutine of Heyfron and Campbell [10] - yield T-counts comparable to or better than the best previously known results.