Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs with 3-nm Gate Length

Abstract

We investigated the device performance of the optimized 3-nm gate length ( L-{G}) bulk silicon FinFET device using 3-D quantum transport device simulation. By keeping source and drain doping constant and by varying only the channel doping, the simulated device is made to operate in three different modes such as inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode. The excellent electrical characteristics of the 3-nm gate length Si-based bulk FinFET device were investigated. The subthreshold slope values (SS \sim 65 mV/decade) and drain-induced barrier lowering (DIBL < 17 mV/V) are analyzed in all three IM, AC, and JL modes bulk FinFET with \vert V-{\rm TH}\vert \sim 0.31 V. Furthermore, the threshold voltage ( V-{\rm TH}) of the bulk FinFET can be easily tuned by varying the work function. This letter reveals that Moore's law can continue up to 3-nm nodes.