256k memory bank design with 9t sram bit cell and 22nm cntfet optimizing for low power and area

Abstract

In this paper, 9T bit cell is designed along with its periphery circuits to enhance the operating speed of 256 Kb memories. 9T SRAM bit cell is designed with 22nm FINFET technology to obtain optimum bit cell transistor geometry. For variations in transistor geometries, VDD and temperature, the leakage current for the designed bit cell is estimated. The peripheral circuitry transistor geometries are designed for applications with low power and high speed. 9T bit cell integrated with its periphery is designed to form 256 Kb memory with two 128 Kb memory banks.