A Hierarchical Design of 128 Bit Carry Lookahead Adder in 65 nm CMOS Technology

Abstract

As One Giga Hertz microprocessors power mobiles, laptops, tablets and personal computers in last few years, there is a massive need to reduce the number cycles to do addition which plays a significant role in Arithmetic Logic Unit (ALU) or Digital Signal Processing (DSP). The complexity of carry propagation is the critical variable once the designs requires addition over 32 bits. A hierarchical design has been developed to find Carry out at 16-bit stage from Propagate and Generate techniques from a 4-bit stage of Carry Lookahead Adder (CLA), so called Carry Lookahead Logic (CLL). Four blocks of CLL have been used to create another CLL block at a 16-bit level and similarly at 64 bit level and 128 bit level. A 65 nm CMOS technology library from Microwind used to simulate from logic to circuit level for the hierarchical design of 128 bit CLA and compared with 90 nm technology