All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part I

Abstract

This two-part paper describes two different techniques for performing analog-to-digital (A/D) conversion compatibly with standard single-channel MOS technology. In the first paper, the use of a binary weighted capacitor array to perform a high-speed, successive approximation conversion is discussed. The technique provides an inherent sample/hold function and can accept both polarities of inputs with a single positive reference. The factors limiting the accuracy and conversion rate of the technique are considered analytically. Experimental results from a monolithic prototype are presented; a resolution of 10 bits was achieved with a conversion time of 23 µs. The estimated die size for a completely monolithic version is 8000 mil2. The second paper [3] describes a two-capacitor successive approximation technique, which, in contrast to the first, requires considerably less die area, is inherently monotonic in the presence of capacitor ratio errors, and which operates at a somewhat lower conversion rate. Factors affecting accuracy and conversion rate are considered analytically. Experimental results from a monolithic prototype are presented; a resolution of 8 bits was achieved with an A/D conversion time of 100 µs. Used as a D/A converter, a settling time of 13.5 µs was achieved. The estimated total die size for a completely monolithic version including logic is 5000 mil2. Copyright © 1975 by The Institute of Electrical and Electronics Engineers, Inc.