A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation

Abstract

Modern integrated circuits such as System-On-Chip (SOC) require a large amount of memory. The integration density of these memories is based on the extreme miniaturization of the technological nodes. However, the miniaturization process contributes to an increase in the occurrence of physical defects. In order to verify the quality of memories, new test methods, based on structural testing, have been proposed recently. However, these methods rely on a digital test environment and require an accurate modeling of the memory. This work proposes a digital SRAM modeling compatible with digital simulation and test environments. The digital SRAM modeling presented in this paper is functionally equivalent to an analog SRAM model (i.e., memorization, Write and Read operations). The memorization capability of the model enables it to consider the data-background of the memory array during testing, facilitating the evaluation of complex test sequences, such as March algorithms, in covering structural fault models (i.e., Cell-Aware fault models).