NoCDAS: A Cycle-Accurate NoC-Based Deep Neural Network Accelerator Simulator

Abstract

Network-on-Chip (NoC) has been widely adopted for Deep Neural Network (DNN) accelerator designs to solve the data communication problem for the large-scale processing element array. As the complexity of these DNN accelerators grows significantly, effective design-space exploration before hardware prototyping becomes crucial. However, the existing simulation tools for NoC-based DNN accelerators are limited in providing accurate hardware microarchitecture representations and execution time analysis. In this article, we present a cycle-accurate simulator for NoC-based DNN accelerators called NoCDAS. The proposed NoCDAS can accurately simulate DNN computation flow on NoC hardware and the correctness of inference output is validated. In addition, NoCDAS supports highly flexible NoC hardware definitions to quantify the end-to-end latency, which allows efficient evaluation of different NoC-based DNN accelerator design parameters. We showcase this ability by running three DNN models on the proposed NoCDAS with various configurations encompassing NoC size, mapping strategy, and core placement.