Optimization of structure and electrical characteristics for four‐layer vertically‐stacked horizontal gate‐all‐around si nanosheets devices

Abstract

In this paper, the optimizations of vertically‐stacked horizontal gate‐all‐around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet‐etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground‐plane (GP) doping in Si sub‐fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n‐type devices were greatly improved with the increase of GP doping doses. However, the p‐type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain‐induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.