An Enhanced Low Power Dual Data Injection Technique for Coarse - Grained Reconfigurable Architecture

Abstract

oarse-gr ained reconfigurable architectures (CGRA) having a well-organized, more efficient configurable array of processing unit and high speed cache unit. The processing unit performs required arithmetic and logic operations. Now a day’s video processing applications power consumption plays an important role. We propose Double Data Rate Synchronous Memory architecture can address and reduce the power consumption caused by reconfiguration. An input data bits are injecting on the data bus in the interval of low to high and high low clock period. All modules have been designed and implemented in vertex using behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.