A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling

Abstract

We propose a charge-domain fractional-N all-digital phase-locked loop (ADPLL) that employs charge-steering sampling (CSS) of a sinusoidal reference waveform. The well-known issue of ΔΣ quantization error in fractional-N operation is compensated by a capacitive digital-to-analog converter (CDAC), which serves the conventional role of a digital-to-time converter (DTC). This CDAC is further merged with the inherent CDAC of a successive approximation register (SAR) analog-to-digital converter (ADC), which is exclusively used for digitizing the time-error mainly induced by the phase noise (PN). Initially, the combined CDACs are preset to VDD , and then discharged during a short digitally controlled oscillator (DCO)-divider-triggered pulse via a pseudo-differential MOS pair directly driven by the input reference sinusoidal waveform. Owing to the gentle slope of the reference waveform, the charge-domain fractional-N operation achieves a wide and linear time-error detection (TD) range. Furthermore, by reinterpreting the SAR ADC output using multi-bit midrise encoding, the effective time-to-digital conversion (TDC) gain is boosted by bang-bang (BB) effects while maintaining fast and robust locking. To accurately model the CSS current, we introduce a damped-sine waveform model incorporating harmonics, providing comprehensive insight into the CSS-TD gain, even with short-channel devices. Fabricated in 22nm CMOS, the prototype achieves an rms jitter of 96fs at 24GHz with a reference spur of −60dBc in integer-N mode, while 167.8fs at approximately 24.5GHz with a worst in-band spur of −47.8dBc in fractional-N mode. The occupied area is only 0.08mm2