New hierarchical algorithm for transistor placement in CMOS macro cell design

Abstract

We have proposed a new algorithm of transistor placement in the layout generation of CMOS macro cell design. In this algorithm, logic gates are extracted from the given net list at the transistor level and hierarchical placement is performed using it as a unit. First, for each logic gate, several candidate transistor placements within a logic gate are generated. Then we determine simultaneously the placement of logic gates and transistor placement inside a logic gate (selection from the candidates) by using the iterative improvement method. In this way, using iterative improvement simultaneously for two layers, a good solution can be obtained within a practicable time. Experiments were performed using a gate array cell library and the results were compared with manual placement by layout designers. Nearly the same quality of placement was achieved with respect to cell width and wire crowding.