A Dynamic Trust Evaluation and Risk Control Mechanism for Heterogeneous Cross-Chain Nodes

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Abstract

Existing cross-chain bridges over-rely on static collateralization and post-event penalties, leaving them vulnerable to concealed on–off attacks and rational group collusion. To address these limitations, this paper proposes a Dynamic Trust Evaluation and Risk Control (DTERC) mechanism for heterogeneous cross-chain relay nodes. First, DTERC develops a multidimensional trust quantification model that combines temporal decay, robust multi-observer latency aggregation, verification accuracy, online stability, and an asymmetric one-strike penalty triggered only by cryptographic evidence. Second, DTERC constructs a threshold-aware N-player evolutionary game model to characterize the k-of-N signature structure of cross-chain relay consensus and introduces a dynamic staking function to reduce the economic incentive for collusion under bounded attack-value and parameter conditions. Third, DTERC designs a threshold-preserving FastPath mechanism to reduce redundant verification for low-risk transactions while retaining committee-level confirmation and challenge-based fallback. The empirical evaluation combines multi-agent simulation, smart-contract prototype testing, whitelist-compromise stress tests, malicious-oracle robustness analysis, network-jitter experiments, repeated trials, and parameter-sensitivity analysis. The results show that, under the tested settings, DTERC reduces the malicious transaction success rate to 0.15% under a 50% initial collusion scenario, lowers core contract Gas overhead by 35.7%, and reduces average end-to-end latency by approximately 10% in benign FastPath conditions. These findings indicate that DTERC improves the security–efficiency trade-off of heterogeneous cross-chain relay networks while making its assumptions and limitations explicit.

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APA

Chen, Z., Liu, H., Zhang, L., & Wu, C. (2026). A Dynamic Trust Evaluation and Risk Control Mechanism for Heterogeneous Cross-Chain Nodes. Computers, 15(6). https://doi.org/10.3390/computers15060390

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