Optimization of power and area in hybrid radix encoding signed multipliers

Abstract

The power optimization has become a great concern due to the increased usage of multimedia devices. The Design alternative is formed by the inexact computing the exploits the error occurrence in various applications and this makes the circuits to reduce energy consumption with small correctness loss. In this paper, we proposed a Hybrid radix Encoding Signed Multipliers that encodes the most significant bits with the accurate radix-4 encoding and the least significant bits with radix-4096. The approximation of radix is performed by rounding the higher radix values to their nearest power of two. Compare with radix- 4 multiplier, the proposed multipliers consumes less energy and the area is reduced. The proposed multipliers in Radix-4096 operations are compared with new incorrect multipliers, and the obtained results are underperforming them in energy consumption. The proposed Hybrid radix Encoding Signed Multiplier is simulated using ModelSim SE6.3f.