Low leakage power SRAM cell for embedded memory

Abstract

Leakage power becomes big percentage of total active power especially for small geometry CMOS technology. It is estimated that 20-50% of total average power during normal operation lost to leakage power. Leakage power is even more important for mobile devices where ideal time is long and battery life is important. This paper presents a low leakage SRAM cell and array architecture targeting high performance, low power embedded memory. The proposed novel 7-Transistor (7T) based memory provides 50% lower leakage power compare to 8T cell and 30% faster access time than traditional 6-Transistor (6T) SRAM cell with increased area of 20% compared to the compact 6T cell. All comparisons are based on 28nm foundry low power process technology. © 2011 IEEE.